Multi-deck memory device including buffer circuitry under array

ABSTRACT

Some embodiments include apparatuses and methods of using the apparatuses. One of the apparatuses includes a substrate, a first deck including first memory cell strings located over the substrate, a second deck including second memory cell strings and located over the first deck, first data lines located between the first and second decks and coupled to the first memory cell strings, second data lines located over the second deck and coupled to the second memory cell strings, and first and second circuitries. The first and second data lines extending in a direction from a first portion of the substrate to a second portion of the substrate. The first buffer circuitry is located in the first portion of the substrate under the first memory cell strings of the first deck and coupled to the first data lines. The second buffer circuitry is located in the second portion of the substrate under the first memory cell strings of the first deck and coupled to the second data lines.

PRIORITY APPLICATION

This application is a continuation of U.S. application Ser. No.16/546,720, filed Aug. 21, 2019, which is incorporated herein byreference in its entirety.

TECHNICAL FIELD

Embodiments described herein generally include memory devices, and morespecifically relate to memory device having multiple decks of memorycells.

BACKGROUND

Memory devices are widely used in computers and many electronic items tostore information. A memory device has numerous memory cells. The memorydevice performs a write operation to store information in the memorycells, a read operation to read the stored information, and an eraseoperation to erase information (e.g., obsolete information) from some orall of the memory cells of the memory device. Memory cells in a memorydevice are usually organized in blocks. A memory device has access linesto access the blocks during a memory operation (e.g., read, write, orerase operation) and data lines to carry information (e.g., in the formof signals) to be stored in or read from the blocks. The memory devicealso has driver circuits to provide signals to circuit elements of theblocks and buffer circuitry to hold information received from or to bestored in memory cells of the blocks. In some conventional memorydevices, the blocks are formed in a single deck. Device performance,device size, or both, are often candidates for improvement considerationin memory devices. However, as described in more details below,incorporating such improvements in some conventional memory devices(e.g., single-deck memory devices) may pose a challenge.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a block diagram of an apparatus in the form of a memorydevice, according to some embodiments described herein.

FIG. 2 shows a schematic diagram of a portion of a memory deviceincluding decks of memory cells of a memory cell block, according tosome embodiments described herein.

FIG. 3 shows a schematic diagram of a portion of the memory device ofFIG. 2 including details of a driver circuit of the memory device andassociated conductive lines coupled to the driver circuit, according tosome embodiments described herein.

FIG. 4 shows a perspective view of a structure of the memory device ofFIG. 2 including some of the memory cell blocks of the memory device,according to some embodiments described herein.

FIG. 5 shows a side view (e.g., cross-sectional view) of a portion ofthe memory device of FIG. 4 including two memory cell blocks of thememory device, according to some embodiments described herein.

FIG. 6 shows another perspective view of the memory device of FIG. 2through FIG. 6 including locations of driver circuits and page buffercircuits of the memory device, according to some embodiments describedherein.

FIG. 7 shows a side view of a structure of a portion of the memorydevice of FIG. 2 through FIG. 6 including more details of pillars and ofmemory cells of a memory cell block of the memory device, according tosome embodiments described herein.

DETAILED DESCRIPTION

The techniques described herein include a memory device having multipledecks of memory cells. The memory device includes a separate page buffercircuitry for a respective deck among the decks of the memory device.Page buffer circuitries of the memory device can be located under amemory array of the memory device. The memory cells of the memory deviceare organized in blocks. Each of the blocks includes portions fromdifferent decks. The memory device includes different driver circuitsfor different blocks. The memory device includes different data lines(e.g., bit lines) for different decks. The data lines of one deck areelectrically separate from data lines of another deck. The memory deviceincludes different sets of access lines (e.g., word lines) for differentblocks. The portions of the same block can share the same set of accesslines. Other structures, operations, and improvements and benefits ofthe memory device are described in detail below with reference to FIG. 1through FIG. 7 .

FIG. 1 shows a block diagram of an apparatus in the form of a memorydevice 100, according to some embodiments described herein. Memorydevice 100 can include a device portion 101 that includes a memory array(or multiple memory arrays) having decks (decks of memory cells) 115 ₀and 115 ₁. In the physical structure of memory device 100, decks 115 ₀and 115 ₁ can be formed vertically (e.g., stacked one over another) overa substrate (e.g., a semiconductor substrate) of memory device 100. Forexample, deck 115 ₀ can be formed over the substrate, and deck 115 ₁ canbe formed over deck 115 ₀. In this example, deck 115 ₁ can be a top deckand deck 115 ₀ can be a bottom deck with respect to the location of thesubstrate.

As shown in FIG. 1 , each of decks 115 ₀ and 115 ₁ can include memorycell strings 130. Each of memory cell strings 130 can include memorycells 102 coupled to each other in series. In the physical structure ofmemory device 100, memory cells 102 in each of memory cell strings 130can be formed in different levels over the substrate of memory device100 (e.g., formed vertically over the substrate of memory device 100).

Memory cell strings 130 can be organized into blocks (memory cellblocks) 190 and 191. Each of blocks 190 and 191 can include a portion ofdeck (e.g., bottom deck) 115 ₀ and a portion of deck (e.g., top deck)115 ₁, such that each of blocks 190 and 191 can include some of memorycell strings 130 from deck 115 ₀, and some of memory cell strings 130from deck 115 ₁.

FIG. 1 shows memory device 100 having two decks 115 ₀ and 115 ₁ and twoblocks 190 and 191 as an example. Memory device 100 can have more thantwo decks of memory cells and more than two memory cell blocks.

As shown in FIG. 1 , memory device 100 can include access lines 150(which can include word lines). Access lines 150 can carry signals(e.g., word line signals) WL0 through WLm. Memory device 100 can useaccess lines 150 to access memory cells 102.

Memory device 100 can include data lines (e.g., top data lines) 170T anddata lines (e.g., bottom data lines) 170B. Data lines 170T can includelocal bit lines for deck 115 ₀. Data lines 170B can include local bitlines for deck 115 ₁. Data lines 170T are electrically separated fromdata lines 170B. Data lines 170T can carry signals (e.g., bit linesignals) BL0 through BLi. Data lines 170B can carry signals (e.g., bitline signals) BL0 through BLj. The number (quantity) of data lines 170Bcan be equal to the number (quantity) of data lines 170T. For example,memory device 100 can include 2^(X) data lines 170T and 2^(X) data lines170B (where X is an integer greater than zero). As an example, X can be16, such that there are 65,536 data lines 170T, and there are 65,536data lines 170B.

As shown in FIG. 1 , memory cell strings 130 of different portions(e.g., top and bottom portions) of each of blocks 190 and 191 can becoupled to respective data lines 170T and 170B. For example, memory cellstrings 130 of the portion (e.g., top portion) of block 190 in deck 115₁ can be coupled to data lines 170T, and memory cell strings 130 of theportion (e.g., bottom portion) of block 190 in deck 115 ₀ can be coupledto data lines 170B. Similarly, memory cell strings 130 of the portion(e.g., top portion) of block 191 in deck 115 ₁ can be coupled to datalines 170T, and memory cell strings 130 of the portion (e.g., bottomportion) of block 191 in deck 115 ₀ can be coupled to data lines 170B.Thus, data lines 170T can be shared by respective portions (e.g., topportions) of blocks 190 and 191. Data lines 170B can be shared byrespective portions (e.g., bottom portions) of blocks 190 and 191.

Memory device 100 can include an address register 107 to receive addressinformation (e.g., address signals) ADDR on lines (e.g., address lines)103. Memory device 100 can include row access circuitry 108 and columnaccess circuitry 109 that can decode address information from addressregister 107. Based on decoded address information, memory device 100can determine which block among the blocks (e.g., blocks 190 and 191) ofmemory device 100 is selected to be accessed during a memory operationand which memory cells (e.g., which of memory cells 102) of the selectedblock are to be accessed during the memory operation.

Memory device 100 can include a control unit 118 that can be configuredto control memory operations of memory device 100 based on controlsignals on lines 104. Examples of the control signals on lines 104include one or more clock signals and other signals (e.g., a chip enablesignal CE #, a write enable signal WE #) to indicate which operation(e.g., read, write, or erase operation) memory device 100 can perform.

Memory device 100 can perform a read operation to read (e.g., sense)information (e.g., previously stored information) from memory cells 102of selected memory cell strings 130 of a selected block among the blocks(e.g., blocks 190 and 191) of memory device 100. Memory device 100 canperform a write (e.g., programming) operation to store (e.g., program)information in memory cells 102 of selected memory cell strings 130 of aselected block among the blocks (e.g., blocks 190 and 191) of memorydevice 100. Memory device 100 can also perform an erase operation toerase information from some or all of memory cells 102 of blocks 190 and191. Control unit 118 can be implemented with (e.g., can include)hardware, firmware, software, or any combination of hardware, firmware,and software that can be configured to allow memory device 100 toperform operations (e.g., read, write, and erase operations) describedherein.

In a read operation, memory device 100 can use data lines 170B to readinformation (e.g., data) from selected memory cell strings 130 of aportion (e.g., bottom portion) in deck 115 ₀ of a selected block (e.g.,one of blocks 190 and 191), and data lines 170T to read information(e.g., data) from selected memory cell strings 130 of a portion (e.g.,top portion) in deck 115 ₁ of a selected block (e.g., one of blocks 190and 191). Information from the selected memory cell strings 130 ofportions (top and bottom portions) in respective decks 115 ₀ and 115 ₁of the selected block can be concurrently (e.g., simultaneously)provided to data lines 170B and 170T.

In a write operation, information (e.g., data) to be stored in selectedmemory cell strings 130 of a portion (e.g., bottom portion) in deck 115₀ of a selected block (e.g., one of blocks 190 and 191) can be based oninformation (e.g., in the form of signals) on data lines 170B, andinformation (e.g., data) to be stored in selected memory cell strings130 of a portion (e.g., top portion) in deck 115 ₁ of a selected block(e.g., one of blocks 190 and 191) can be based on information (e.g., inthe form of signals) on data lines 170T. Information can be concurrently(e.g., simultaneously) stored in selected memory cell strings 130 of theportions (top and bottom portions) in respective decks 115 ₀ and 115 ₁of the selected block.

Memory device 100 can include buffer circuitry (e.g., left buffercircuitry) 120L and buffer circuitry (e.g., right buffer circuitry)120R. Buffer circuitry 120L can be coupled to data lines 170B. Buffercircuitry 120R can be coupled to data lines 170T. Each of buffercircuitries 120L and 120R can include components, for example, senseamplifiers and page buffer circuits (e.g., data latches).

Buffer circuitry 120L can be configured to determine (e.g., by sensing)and store (e.g., temporarily store) the value of information read fromselected memory cell strings 130 of a portion (e.g., bottom portion) ofa selected block (e.g., one of blocks 190 and 191) in deck 115 ₀. Buffercircuitry 120L can store (e.g., temporary store) information (e.g.,write data during a write operation) that is to be stored in a portion(e.g., top portion) in deck 115 ₁ of blocks 190 and 191.

Similarly, buffer circuitry 120R can be configured to determine (e.g.,by sensing) and store (e.g., temporarily store) the value of informationread from selected memory cell strings 130 of a portion (e.g., topportion) of a selected block (e.g., one of blocks 190 and 191) in deck115 ₁. Buffer circuitry 120R can store (e.g., temporarily store)information (e.g., write data during a write operation) that is to bestored in a portion (e.g., top portion) of blocks 190 and 191.

Memory device 100 can include input/output (I/O) circuitry 117 that canrespond to signals SEL_0 through SEL_k from column access circuitry 109during a read and write operation. During a read operation, buffercircuitries 120L and 120R can provide (e.g., pass) information read froma selected block (e.g., one of blocks 190 and 191) to I/O circuitry 117through lines (e.g., internal bus) 175L and lines (e.g., internal bus)175R, respectively. During a write operation, I/O circuitry 117 canselectively provide information (to be stored in a select block) tobuffer circuitries 120L and 120R.

Memory device 100 can include lines (e.g., I/O lines) 105. Signals DQ0through DQN on lines 105 can represent information read from or storedin memory cells 102 of decks 115 ₀ and 115 ₁. Lines 105 can includenodes within memory device 100 or pins (or solder balls) on a package ofmemory device 100. Other devices external to memory device 100 (e.g., amemory controller or a processor) can communicate with memory device 100through lines 103, 104, and 105.

Memory device 100 can receive a supply voltage, including supplyvoltages Vcc and Vss. Supply voltage Vss can operate at a groundpotential (e.g., having a value of approximately zero volts). Supplyvoltage Vcc can include an external voltage supplied to memory device100 from an external power source such as a battery or an alternatingcurrent to direct current (AC-DC) converter circuitry.

Each of memory cells 102 can be programmed to store informationrepresenting a value of a fraction of a bit, a value of a single bit, ora value of multiple bits such as two, three, four, or another number ofbits. For example, each of memory cells 102 can be programmed to storeinformation representing a binary value “0” or “1” of a single bit. Thesingle bit per cell is sometimes called a single level cell. In anotherexample, each of memory cells 102 can be programmed to store informationrepresenting a value for multiple bits, such as one of four possiblevalues “00”, “01”, “10”, and “11” of two bits, one of eight possiblevalues “000”, “001”, “010”, “011”, “100”, “101”, “110”, and “111” ofthree bits, or one of other values of another number of multiple bits. Acell that has the ability to store multiple bits is sometimes called amulti-level cell (or multi-state cell).

Memory device 100 can include a non-volatile memory device, and memorycells 102 can include non-volatile memory cells, such that memory cells102 can retain information stored thereon when power (e.g., voltage Vcc,Vss, or both) is disconnected from memory device 100. For example,memory device 100 can be a flash memory device, such as a NAND flash(e.g., 3-dimensional (3-D)) NAND) or a NOR flash memory device, oranother kind of memory device, for example, a variable resistance memorydevice (e.g., a phase change memory device or a resistive RAM (RandomAccess Memory) device).

One of ordinary skill in the art may recognize that memory device 100may include other components, several of which are not shown in FIG. 1so as not to obscure the example embodiments described herein. At leasta portion of memory device 100 can include structures and operationssimilar to or identical to any of the memory devices described belowwith reference to FIG. 2 through FIG. 7 .

FIG. 2 shows a schematic diagram of a portion of a memory device 200including decks (decks of memory cells) 215 ₀ and 215 ₁ and a block(memory cell block) 290, according to some embodiments described herein.Memory device 200 can correspond to memory device 100 of FIG. 1 . Forexample, decks 215 ₀ and 215 ₁ can correspond to decks 115 ₀ and 115 ₁,respectively, of FIG. 1 , and block 290 can correspond to block 190 ofFIG. 1 . In another example, memory device 200 can include a controlunit (not shown) that can correspond to control unit 118 of FIG. 1 . Thecontrol unit of memory device 200 can be implemented with (e.g., caninclude) firmware, software, or any combination of hardware, firmware,and software that can be configured to allow memory device 200 toperform operations (e.g., read, write, and erase operations) describedherein.

FIG. 2 shows directions (e.g., dimension) X, Y, and Z to indicate that,in the physical structure of memory device 200 (shown in FIG. 4 throughFIG. 7 ), decks 215 ₀ and 215 ₁ can be located (e.g., formed) one overanother over a substrate (e.g., a semiconductor substrate) in theZ-direction (e.g., arranged vertically over the substrate). TheZ-direction is perpendicular to the X-direction and Y-direction(perpendicular to an X-Y plane).

As shown in FIG. 2 , block 290 can include a portion (e.g., top portion)290 ₁ that is part of deck 215 ₁ and a portion (e.g., bottom portion)290 ₀ that is part of deck 215 ₀. For simplicity, FIG. 2 shows aschematic diagram of one block (e.g., block 290) of memory device 200.However, memory device 200 can also include additional blocks that areomitted from FIG. 2 . For example, FIG. 4 (described below) shows astructure of memory device 200 including blocks (four blocks) 290, 291,292, and 293. The other blocks (e.g., blocks 291, 292, and 293 in FIG. 4) of memory device 200 can include elements similar to the memoryelements of block 290 schematically shown in FIG. 2 .

Memory device 200 can include access lines (a set of access lines) 250,251, 252, and 253 that can carry corresponding signals (e.g., word linesignals) WL0, WL1, WL2, and WL3. Each of access lines 250, 251, 252, and253 can be structured as a conductive line. Access lines 250, 251, 252,and 253 can include word lines of memory device 200. Memory device 200can use the same set of access line (e.g., access lines 250, 251, 252,and 253) to access (e.g., concurrently) access portions 290 ₀ and 290 ₁of block 290.

As shown in FIG. 2 , deck 215 ₀ can include control gates (e.g., memorycell control gates) 240 ₀, 241 ₀, 242 ₀, and 243 ₀ in portion 290 ₀ ofblock 290. Control gates 240 ₀, 241 ₀, 242 ₀, and 243 ₀ can be coupledto (or can be part of) access lines 250, 251, 252, and 253,respectively. Deck 215 ₁ can include control gates (e.g., memory cellcontrol gates) 240 ₁, 241 ₁, 242 ₁, and 243 ₁ in portion 290 ₁ of block290. Control gates 240 ₁, 241 ₁, 242 ₁, and 243 ₁ can be coupled to (orcan be part of) access lines 250, 251, 252, and 253, respectively.

Portions 290 ₀ and 290 ₁ of block 290 can share the same access lines(e.g., access lines 250, 251, 252, and 253), such that control gates ofportions 290 ₀ and 290 ₁ that have the same relative position in decks215 ₀ and 215 ₁ can share the same access (e.g., can be coupled to thesame access line) to receive the same signal (e.g., the same word linesignal). For example, as shown in FIG. 2 , control gates 240 ₀ and 240 ₁can be coupled to the same access line (e.g., access line 250) toreceive the same signal (e.g., signal WL0). Control gates 241 ₀ and 241₁ can be coupled to the same access line (e.g., access line 251) toreceive the same signal (e.g., signal WL1). Control gates 242 ₀ and 242₁ can be coupled to the same access line (e.g., access line 252) toreceive the same signal (e.g., signal WL2). Control gates 243 ₀ and 243₁ can be coupled to the same access line (e.g., access line 253) toreceive the same signal (e.g., signal WL3).

As shown in FIG. 2 , deck 215 ₀ can include data lines 270 ₀, 271 ₀, and272 ₀ that carry signals (e.g., bit line signals) BL0 ₀, BL1 ₀, and BL2₀, respectively. Each of data lines 270 ₀, 271 ₀, and 272 ₀ can bestructured as a conductive line that can include a bit line (e.g., localbit line) of deck 215 ₀. Each of data lines 270 ₀, 271 ₀, and 272 ₀ canhave a length extending in the X-direction. Thus, the Y-direction can beperpendicular to the length of each data line 270 ₀, 271 ₀, and 272 ₀.Deck 215 ₁ can include data lines 270 ₁, 271 ₁, and 272 ₁ that carrysignals (e.g., bit line signals) BL0 ₁, BL1 ₁, and BL2 ₁, respectively.Each of data lines 270 ₁, 271 ₁, and 272 ₁ can be structured as aconductive line that can include a bit line (e.g., local bit line) ofdeck 215 ₁. Each of data lines 270 ₁, 271 ₁, and 272 ₁ can have a lengthextending in the X-direction. Thus, the Y-direction can be perpendicularto the length of each data line 270 ₁, 271 ₁, and 272 ₁.

FIG. 2 shows each of deck 215 ₀ and 215 ₁ including three data lines,four control gates, and four access line as an example. The number ofdata lines, control gates, and access lines of memory device 200 canvary.

As mentioned above, FIG. 2 omits other blocks (e.g., blocks 291, 292,and 293 shown in FIG. 4 ) of memory device 200. However, a portion(e.g., bottom portion) of each of other blocks (e.g., blocks 291, 292,and 293 shown in FIG. 4 ) of memory device 200 can share (e.g., can becoupled to) data lines 270 ₀, 271 ₀, and 272 ₀ with portion 290 ₀ ofblock 290. A portion (e.g., top portion) of each of other blocks (e.g.,blocks 291, 292, and 293 shown in FIG. 4 ) of memory device 200 canshare (e.g., can be coupled to) data lines 270 ₁, 271 ₁, and 272 ₁ withportion 290 ₁ of block 290.

As shown in FIG. 2 , data lines 270 ₀, 271 ₀, and 272 ₀ of deck 215 ₀are separated from and not coupled to (e.g., electrically unconnectedto) data lines 270 ₁, 271 ₁, and 272 ₁ of deck 215 ₁. Thus, during aread operation performed on block 290, memory device 200 can use datalines 270 ₀, 271 ₀, and 272 ₀ to carry information read from memorycells in portion 290 ₀ of block 290, and data lines 270 ₁, 271 ₁, and272 ₁ to carry information read from memory cells in portion 290 ₁ ofblock 290. Thus, data lines 270 ₀, 270 ₁, 271 ₀, 271 ₁, 272 ₀, and 272 ₁can concurrently (e.g., simultaneously) carry information read fromrespective portions 290 ₀ and 290 ₁ of block 290. In a write operationperformed on block 290, information to be concurrently stored inportions 290 ₀ and 290 ₁ of block 290 can be based on the information onrespective data lines 270 ₀, 270 ₁, 271 ₀, 271 ₁, 272 ₀, and 272 ₁.

As shown in FIG. 2 , decks 215 ₀ and 215 ₁ have similar elements. Thus,for simplicity, similar elements between decks 215 ₀ and 215 ₁ are giventhe same designation labels (e.g., reference numbers). The followingdescription focuses on details of portion (e.g., bottom portion) 290 ₀of block 290. The elements of portion (e.g., top portion) 290 ₁ of block290 can have a similar description (which is not described in detailbelow for simplicity).

As shown in FIG. 2 , portion 290 ₀ of block 290 includes memory cells210, 211, 212, and 213; select transistors (e.g., source selecttransistors) 261, 262, and 263; and select transistors (e.g., drainselect transistors) 264, 265, and 266. Memory cells 210, 211, 212, and213 can be arranged in memory cell strings, such as memory cell strings231 through 239. Deck 215 ₀ can include a line 299 ₀ that can carry asignal SRC) (e.g., source line signal). Line 299 ₀ can be structured asa conductive region (e.g., conductive line or alternatively a conductiveplate) that can form part of a source (e.g., a source line oralternatively a source plate) of deck 215 ₀ of memory device 200.

Each of memory cell strings 231 through 239 of portion 290 ₀ of block290 (located in deck 215 ₀) can be coupled to one of data lines 270 ₀,271 ₀, and 272 ₀ through one of select transistors 264, 265, and 266.Each of memory cell strings 231 through 239 of portion 290 ₀ of block290 can also be coupled to line 299 ₀ through one of select transistors261, 262, and 263. For example, memory cell string 231 can be coupled todata line 270 ₀ through select transistor 264 (directly over memory cellstring 231) and to line 299 ₀ through select transistor 261 (directlyunder memory cell string 231). In another example, memory cell string232 can be coupled to data line 270 ₀ through select transistor 265(directly over memory cell string 232) and to line 299 ₀ throughtransistor 262 (directly under memory cell string 232). FIG. 2 shows anexample of nine memory cell strings 231 through 239 and four memorycells 210, 211, 212, and 213 in each memory cell string. However, thenumber of memory cell strings and the number of memory cells in eachmemory cell string of portion 290 ₀ of block 290 can vary.

As shown in FIG. 2 , some memory cells (e.g., memory cells 213) ofdifferent memory cell strings (e.g., memory cell strings 231 through239) can be controlled by the same control gate (e.g., control gate 243₀) and can be coupled to the same access line (e.g., access line 253).Some other memory cells (e.g., memory cells 212) of these memory cellstrings (e.g., memory cell strings 231 through 239) can be controlled byanother control gate (e.g., control gate 242 ₀). Each of control gates240 ₀, 241 ₀, 242 ₀, and 243 ₀ can be structured as a single conductiveplate (shown in FIG. 4 through FIG. 7 ). During a memory operationperformed on block 290 of memory device 200, control gates 240 ₀, 241 ₀,242 ₀, and 243 ₀ can receive respective signals WL0, WL1, WL2, and WL3(through respective access lines 250, 251, 252, and 253) to accessmemory cells 210, 211, 212, and 213 of selected memory cell stringsamong memory cell strings 231 through 239 of portion 290 ₀ of block 290.

As shown in FIG. 2 , select transistors 261, 262, and 263 of portion 290₀ of block 290 can be coupled to a select line (e.g., source selectline) 280, and can be controlled (e.g., turned on or turned off) by thesame signal, such as an SGS signal (e.g., source select gate signal)applied to select line 280. During a memory operation (e.g., a read orwrite operation) performed on block 290, select transistors 261, 262,and 263 can be turned on (e.g., by activating the SGS signal) to couplememory cell strings 231 through 239 of portion 290 ₀ of block 290 toline 299 ₀. Select transistors 261, 262, and 263 of portion 290 ₀ ofblock 290 can be turned off (e.g., by deactivating the SGS signal) todecouple memory cell strings 231 through 239 of portion 290 ₀ of block290 from line 299 ₀.

Select transistors 264, 265, and 266 of portion 290 ₀ of block 290 canbe coupled to select lines (e.g., drain select lines) 284, 285, and 286,respectively, and can be controlled (e.g., turned on or turned off) bycorresponding signals SGD0, SGD1, and SGD2 (e.g., drain select gatesignals). During a memory operation (e.g., a read or write operation)select transistors 264, 265, and 266 can be selectively turned on (e.g.,by selectively activating signals SGD0, SGD1, and SGD2) to selectivelycouple the memory cell strings of portion 290 ₀ of block 290 to theirrespective data lines 270 ₀, 271 ₀, and 272 ₀. Select transistors 264,265, and 266 of portion 290 ₀ of block 290 can be selectively turned off(e.g., by selectively deactivating signals SGD0, SGD1, and SGD2) toselectively decouple the memory cell strings of portion 290 ₀ of block290 from their respective data lines 270 ₀, 271 ₀, and 272 ₀.

During a memory operation (e.g., a read or write operation), only one ofthe signals SGD0, SGD1, and SGD2 can be activated at a time (e.g., thesignals can be sequentially activated). For example, during a readoperation to read (e.g., sense) information from memory cell strings231, 234, and 237, signal SGD0 can be activated to turn on transistors264 of portion 290 ₀ of block 290 and couple memory cell strings 231,234, and 237 of portion 290 ₀ of block 290 to data lines 270 ₀, 271 ₀,and 272 ₀, respectively. In this example, signals SGD1 and SGD2 can bedeactivated (while signal SGD0 is activated) to decouple memory cellstrings 232, 235, 238, 233, 236, and 239 of portion 290 ₀ of block 290from data lines 270 ₀, 271 ₀, and 272 ₀. In another example, during aread operation to read information from memory cell strings 232, 235,and 238, signal SGD1 can be activated to turn on transistors 265 ofportion 290 ₀ of block 290 and couple memory cell strings 232, 235, and238 of portion 290 ₀ of block 290 to data lines 270 ₀, 271 ₀, and 272 ₀,respectively. In this example, signals SGD0 and SGD2 can be deactivated(while signal SGD1 is activated) to decouple memory cell strings 231,234, 237, 233, 236, and 239 of portion 290 ₀ of block 290 from datalines 270 ₀, 271 ₀, and 272 ₀.

As mentioned above, portion 290 ₁ of block 290 in deck 215 ₁ includeselements similar to those of portion 290 ₀ of block 290 in deck 215 ₀.For example, as shown in FIG. 2 , portion 290 ₁ of block 290 in deck 215₁ can include memory cell strings 231 through 239; select transistors(e.g., source select transistors) 261, 262, and 263; select transistors(e.g., drain select transistors) 264, 265, and 266; select line (e.g.,source select line) 280 and corresponding signal SGS (e.g., sourceselect gate signal); line 299 ₁ (e.g., source line, source region, orsource plate) and corresponding signal (e.g., source line signal) SRC₁;select lines (e.g., drain select lines) 284, 285, and 286 andcorresponding signals (e.g., drain select gate signals) SGD0, SGD1, andSGD2.

Portions 290 ₀ and 290 ₁ of block 290 can share the same select lines(e.g., source select line 280 and drain select lines 284, 285, and 286).For example, FIG. 2 shows the same labels for select lines (e.g., drainselect lines) 284, 285, and 286 and for signals SGD0, SDG1, and SDG2, inboth portions 290 ₀ and 290 ₁ of block 290 to indicate that portions 290₀ and 290 ₁ can share select lines 284, 285, and 286 and signals SGD0,SDG1, and SDG2. In another example, FIG. 2 shows the same label forselect line (e.g., source select line) 280 and for signal SGS in bothportions 290 ₀ and 290 ₁ of block 290 to indicate that portions 290 ₀and 290 ₁ can share select line 280 and signal SGS.

Thus, select lines 284, 285, and 286 of portion 290 ₀ can be coupled to(e.g., electrically in contact with) select lines 284, 285, and 286 ofportion 290 ₁, respectively. Select line 280 of portion 290 ₀ can becoupled to (e.g., electrically in contact with) select line 280 ofportion 290 ₁. For simplicity, FIG. 2 omits the connections (e.g.,connecting lines) between select lines 284, 285, and 286 of portion 290₀ and select lines 284, 285, and 286 of portion 290 ₁, respectively, andomits a connection between select line 280 of portion 290 ₀ and selectline 280 of portion 290 ₁.

Since portions 290 ₀ and 290 ₁ of block 290 can share the same selectlines (e.g., source select line 280 and drain select lines 284, 285, and286), select transistors (e.g., source select transistors) 261, 262, and263 of portions 290 ₀ and 290 ₁ can be coupled to the same select line(e.g., source select line 280) to receive the same signal (e.g., signalSGS).

Similarly, select transistors (e.g., drain select transistors) 264 ofportions 290 ₀ and 290 ₁ can be coupled to the same select line (e.g.,select line 284) to receive the same signal (e.g., signal SGD0). Selecttransistors (e.g., drain select transistors) 265 of portions 290 ₀ and290 ₁ can be coupled to the same select line (e.g., drain select line285) to receive the same signal (e.g., signal SGD1). Select transistors(e.g., drain select transistors) 266 of portions 290 ₀ and 290 ₁ can becoupled to the same select line (e.g., drain select line 286) to receivethe same signal (e.g., signal SGD2).

As shown in FIG. 2 , different memory cell strings in the X-direction(e.g., memory cell strings coupled to different drain select lines) inportion 290 ₀ can share a data line among data lines 270 ₀, 271 ₀, and272 ₀. For example, in portion 290 ₀, memory cell strings 231, 232, and233 can share data line 270 ₀. Memory cell strings 234, 235, and 236 canshare data line 271 ₀. Memory cell strings 237, 238, and 239 can sharedata line 272 ₀.

However, memory cell strings within the same group in the Y-direction(e.g., memory cell strings coupled to the same drain select line) inportion 290 ₀ may not share a data line (e.g., may be coupled to aseparate data line). For example, in portion 290 ₀, memory cell strings231, 234, and 237 can be coupled to data lines 270 ₀, 271 ₀, and 272 ₀,respectively, such that memory cell strings 231, 234, and 237 may notshare data lines 270 ₀, 271 ₀, and 272 ₀. In another example, in portion290 ₀, memory cell strings 232, 235, and 238 can be coupled to datalines 270 ₀, 271 ₀, and 272 ₀, respectively, such that memory cellstrings 232, 235, and 238 may not share data lines 270 ₀, 271 ₀, and 272₀.

Similarly, different memory cell strings in the X-direction (e.g.,memory cell strings coupled to different drain select lines) in portion290 ₁ can share a data line among data lines 270 ₁, 271 ₁, and 272 ₁.However, memory cell strings within the same group in the Y-direction(e.g., memory cell strings coupled to the same drain select line) inportion 290 ₁ may not share a data line (e.g., may be coupled to aseparate data line).

As shown in FIG. 2 , memory device 200 can include a driver circuit(e.g., string driver circuit) 240; buffer circuitry 220R and 220L;conductive paths 270′₀, 271′₀, and 272′₀ coupled to (e.g., coupleddirectly between) buffer circuitry 220L and data lines 270 ₀, 271 ₀, and272 ₀, respectively; conductive paths 270′₁, 271′₁, and 272′₁ coupled to(e.g., coupled directly between) buffer circuitry 220R and data lines270 ₁, 271 ₁, and 272 ₁, respectively; and an input/output circuitry217. Conductive paths 270′₀, 271′₀, and 272′₀ can be considered as partof data lines 270 ₀, 271 ₀, and 272 ₀, respectively. Conductive paths270′₁, 271′₁, and 272′₁ can be considered as part of data lines 270 ₁,271 ₁, and 272 ₁, respectively. Each of conductive paths 270′₀, 271′₀,272′₀, 270′₁, 271′₁, and 272′₁ can have a length extending in adirection (e.g., Z-direction) from deck 215 ₀ to deck 215 ₁ (e.g.,extending vertically in the Z-direction).

Thus, as shown in FIG. 2 , no deck among the decks (e.g., 215 ₀ and 215₁) of memory device 200 shares a data line (or data lines) of the datalines (e.g., 270 ₀, 271 ₀, 272 ₀, 270 ₁, 271 ₁, and 272 ₁) of memorydevice 200 with another deck among the decks of memory device 200. Forexample, decks 215 ₀ and 215 ₁ share no data line (do not share a dataline or data lines) among data lines 270 ₀, 271 ₀, 272 ₀, 270 ₁, 271 ₁,and 272 ₁ and share no conductive path (do not share a conductive pathor conductive paths) among conductive paths 270′₀, 271′₀, 272′₀, 270′₁,271′₁, and 272′₁.

Driver circuit 240 can be part of row access circuitry of memory device200 that can correspond to row access circuitry 108 of FIG. 1 . Memorydevice 200 can include a separate driver circuit for each block ofmemory device 200. Thus, in memory device 200, the number of drivercircuits (e.g., string driver circuits) can be equal to the number ofblocks of memory device 200. For example, memory device 200 can include1024 driver circuits and 1024 blocks. Each of the driver circuits ofmemory device 200 can be controlled by (e.g., can respond to) a separatesignal (e.g., a separate block select signal).

As shown in FIG. 2 , driver circuit 240 can receive a signal (e.g.,block select signal) BLK_SEL. During an operation (e.g., read, write, orerase operation) of memory device 200, driver circuit 240 can operate toapply voltages to the signals on access lines 250, 251, 252, and 253,select lines (e.g., drain select lines) 284, 285, and 286, and selectline (e.g., source select line) 280. A decoder (e.g., decoder includedin a row access circuitry) of memory device 200 can decode addressinformation to determine which block among the blocks of memory device200 is to be accessed during an operation of memory device 200. Thedecoder circuit of memory device 200 can activate signal BLK_SEL whenblock 290 is selected during a read, write, or erase operation of memorydevice 200.

Buffer circuitries 220L and 220R can be part of the buffer circuitry ofmemory device 200 that can correspond to and operate in ways similar to(or the same as) buffer circuitries 120L and 120R, respectively, of FIG.1 . As shown in FIG. 2 , buffer circuitry 220L can include buffercircuits (e.g., page buffer circuits) 220L.0, 220L.1, and 220L.2 coupledto data lines 270 ₀, 271 ₀, and 272 ₀, respectively. Each of buffercircuits 220L.0, 220L.1, and 220L.2 can include a sense amplifier tosense information (e.g., in the form of a signal) on a respective dataline (among data lines 270 ₀, 271 ₀, and 272 ₀) and a data latch stores(e.g., temporarily stores) one bit (or multiple bits) of informationcarried by the respective data line. FIG. 2 shows three buffer circuits220L.0, 220L.1, and 220L.2 as an example. However, the number of buffercircuits of buffer circuitry 220L can be equal to the number of datalines of deck 215 ₀. For example, if the number of data lines of deck215 ₀ is 65,536, then the number of buffer circuits of buffer circuitry220L can also be 65,536.

Similarly, buffer circuitry 220R can include buffer circuits (e.g., pagebuffer circuits) 220R.0, 220R.1, and 220R.2 coupled to data lines 270 ₁,271 ₁, and 272 ₁, respectively. Each of buffer circuits 220R.0, 220R.1,and 220R.2 can include a sense amplifier to sense information (e.g., inthe form of a signal) on a respective data line (among data lines 270 ₁,271 ₁, and 272 ₁) and a data latch stores (e.g., temporarily stores) onebit (or multiple bits) of information carried by the respective dataline. FIG. 2 shows three buffer circuits 220R.0, 220R.1, and 220R.2 asan example. However, the number of buffer circuits of buffer circuitry220R can be equal to the number of data lines of deck 215 ₁. Forexample, if the number of data lines of deck 215 ₁ is 65,536, then thenumber of buffer circuits of buffer circuitry 220R can also be 65,536.The number of buffer circuits of buffer circuitry 220R can be equal tothe number of buffer circuits of buffer circuitry 220L.

During a read operation, information from selected memory cell strings130 of portions 290 ₀ and 290 ₁ of block 290 can be concurrently (e.g.,simultaneously) provided to buffer circuitries 220L and 220R,respectively, through data lines 170B and 170T, respectively. Forexample, information from data lines 270 ₀, 271 ₀, and 272 ₀ during aread operation can be concurrently (e.g., simultaneously) provided tobuffer circuits 220L.0, 220L.1, and 220L.2, respectively. Informationfrom data lines 270 ₁, 271 ₁, and 272 ₁ can be concurrently (e.g.,simultaneously) provided to buffer circuits 220R.0, 220R.1, and 220R.2,respectively, while information from data lines 270 ₀, 271 ₀, and 272 ₀is concurrently provided to buffer circuits 220L.0, 220L.1, and 220L.2,respectively.

During a write operation, information can be concurrently (e.g.,simultaneously) stored in portions 290 ₀ and 290 ₁ of block 290.Information to be stored in portion 290 ₀ can be based in information inbuffer circuitry 220L. Information to be stored in portion 290 ₁ can bebased on information in buffer circuitry 220R.

Input/output (I/O) circuitry 217 of memory device 200 can correspond toand operate in ways similar to (or the same as) input/output circuitry117 of FIG. 1 . For example, during a read operation of memory device200, I/O circuitry 217 can selectively receive information (e.g.,information read from block 290) from buffer circuitries 120L and 120R.During a write operation, I/O circuitry 217 can selectively provideinformation (information to be stored in block 290) to buffercircuitries 120L and 120R. During a read operation, buffer circuitries220L and 220R can provide (e.g., pass) information read from block 290to I/O circuitry 217. During a write operation, I/O circuitry 217 canselectively provide information (to be stored in a select block) tobuffer circuitries 220L and 220R.

Memory device 200 can be configured such that information from buffercircuitries 220L and 220R during a read operation can be provided to I/Ocircuitry 217 in one of many different ways. In an example configurationof memory device 200, bits of information from buffer circuitry 220Rduring a read operation can be passed to I/O circuitry 217 before bitsof information from buffer circuitry 220L can be passed to I/O circuitry217. In this example configuration, B bits at a time can be passed(e.g., using a multiplexer in I/O circuitry 217 or in buffer circuitry220R) from buffer circuitry 220R to I/O circuitry 217 until all bits ofinformation from buffer circuitry 220R are passed to I/O circuitry 217.B is an integer greater than one (e.g., B=8, 16, 32 or another number)and less than the number of buffer circuits of each of buffercircuitries 220L and 220R. B can be the bandwidth of an internal bus(e.g., B-bitwide bus) between I/O circuitry 217 and each of buffercircuitries 220R and 220L. In this example configuration, the bits ofinformation from buffer circuitry 220L during a read operation can bepassed to I/O circuitry 217 after all bits of information from buffercircuitry 220R are passed to I/O circuitry 217. For example, B bits at atime can be passed (e.g., using a multiplexer in I/O circuitry 217 or inbuffer circuitry 220L) from buffer circuitry 220L to I/O circuitry 217until all bits of information from buffer circuitry 220L are passed toI/O circuitry 217.

In another example configuration of memory device 200, bits ofinformation from buffer circuitry 220L during a read operation can bepassed to I/O circuitry 217 before bits of information from buffercircuitry 220R can be passed to I/O circuitry 217. In this exampleconfiguration, B bits at a time can be passed (e.g., using a multiplexerin I/O circuitry 217 or in buffer circuitry 220R) from buffer circuitry220L to I/O circuitry 217 until all bits of information from buffercircuitry 220L are passed to I/O circuitry 217. In this exampleconfiguration, the bits of information from buffer circuitry 220R duringa read operation can be passed to I/O circuitry 217 after all bits ofinformation from buffer circuitry 220L are passed to I/O circuitry 217.For example, B bits at a time can be passed from buffer circuitry 220Rto I/O circuitry 217 until all bits of information from buffer circuitry220R are passed to I/O circuitry 217.

In another example configuration, bits of information during a readoperation from buffer circuitries 220L and 220R can be alternatelypassed (e.g., passed in an interleave fashion) to the I/O circuitry 217.For example, S bit (or S bits) from buffer circuitry 220R can be passedto I/O circuitry 217, then S bit (or S bits) from buffer circuitry 220Lcan be passed to I/O circuitry 217, where S is an integer equal to orgreater than one. In this example, S bit (or S bits) at a time from eachof buffer circuitries 220L and 220R can be alternately passed to I/Ocircuitry 217 until all bits of information from buffer circuitries 220Land 220R are passed to I/O circuitry 217. In this example configuration,S bit (or S bits) from either buffer circuitry 220L or buffer circuitry220R can be selected as the first bit (or bits) to be passed to I/Ocircuitry 217.

Memory device 200 can be configured such that information to be storedin block 290 in a write operation can be provided to buffer circuitries220L and 220R in one of many different ways. For example, memory device200 can be configured to have any of the example configurationsdescribed above for a read operation but in a reverse manner.

As an example, information to be stored in portion 290 ₁ of block 290during a write operation can be passed B bits at a time from I/Ocircuitry 217 to buffer circuitry 220R. Information to be stored inportion 290 ₀ of block 290 during a write operation can be passed B bitsat a time from I/O circuitry 217 to buffer circuitry 220L. In thisexample, information to be stored in portion 290 ₀ of block 290 can bepassed from I/O circuitry 217 to buffer circuitry 220L after informationto be stored in portion 290 ₁ of block 290 are passed from I/O circuitry217 to buffer circuitry 220R. Alternatively, information to be stored inportion 290 ₁ of block 290 can be passed from I/O circuitry 217 tobuffer circuitry 220R after information to be stored in portion 290 ₀ ofblock 290 are passed from I/O circuitry 217 to buffer circuitry 220L.

In another example, information to be stored in block 290 during a writeoperation can be alternately passed (e.g., passed in an interleavefashion) from I/O circuitry 217 to buffer circuitries 220L and 220R. Forexample, S bit (or S bits) among the bits of information to be stored inportion 290 ₁ of block can be passed from I/O circuitry 217 to buffercircuitry 220R, and S bit (or S bits) among the bits of information tobe stored in portion 290 ₀ of block 290 can be passed from I/O circuitry217 to buffer circuitry 220L in an interleave fashion. In this example,I/O circuitry 217 can be configured to pass S bit (or S bits) to beeither buffer circuitry 220L or buffer circuitry 220R as the first bit(or bits).

A memory cell block (e.g., block 290) of a memory device (e.g., memorydevice 200) described herein is a group of memory cells (e.g., memorycells 210, 211, 212, and 213 of block 290) in which fewer than all ofthe memory cells (or alternatively all of the memory cells) in the groupof memory cells can be selected to store information (e.g., in a writeoperation) in or read information (e.g., in a read operation) from theselected memory cells. However, in an erase operation, all of the memorycells in the group of memory cells (e.g., memory cells 210, 211, 212,and 213 of block 290) are selected (e.g., automatically selected) evenif some of the memory cells in the group of memory cells are availableto store information (e.g., some of the memory cells in the group ofmemory cells have no stored information before the erase operation).Further, a memory cell block (e.g., block 290) of a memory device (e.g.,memory device 200) described herein is a group of memory cells (e.g.,memory cells 210, 211, 212, and 213 of block 290) that can have the sameblock address.

In a memory operation (e.g., read operation), memory device 200 canoperate to concurrently (simultaneously) establish circuit paths (e.g.,current paths) between data lines 270 ₀, 271 ₀, and 272 ₀ and buffercircuitry 220L (e.g., through respective conductive paths 270′₀, 271′₀,and 272′₀), and concurrently establish circuit paths (e.g., currentpaths) between data lines 270 ₁, 271 ₁, and 272 ₁ and buffer circuitry220R (e.g., through respective conductive paths 270′₁, 271′₁, and272′₁). Thus, circuit paths between data lines 270 ₀, 271 ₀, and 272 ₀and buffer circuitry 220L and the circuit paths between data lines 270₁, 271 ₁, and 272 ₁ and buffer circuitry 220R can be concurrentlyestablished.

In an example operation of memory device 200, portions 290 ₀ and 290 ₁can be concurrently selected (e.g., selected at the same time) tooperate on memory cells 210, 211, 212, and 213 of portions 290 ₀ and 290₁. In this example, memory device 200 can access and store informationin selected memory cells of each of portions 290 ₀ and 290 ₁ (e.g., ifthe operation is a write operation), read information from selectedmemory cells of each of portions 290 ₀ and 290 ₁ (e.g., if the operationis a read operation), or erase information from selected memory cells(e.g., or from all of memory cells) of each of portions 290 ₀ and 290 ₁(e.g., if the operation is an erase operation).

Thus, as described above, memory device 200 can include separate datalines for different decks (e.g., data lines 270 ₀, 271 ₀, and 272 ₀ fordeck 215 ₀, and data lines 270 ₁, 271 ₁, and 272 ₁ for deck 215 ₁), thesame driver circuit (e.g., driver circuit 240) for different portions(e.g., portions 290 ₀ and 290 ₁) of block 290, and separate (e.g.,dedicated) buffer circuitries (e.g., 220L and 220R) for different datalines 270 ₀, 271 ₀, and 272 ₀, and data lines 270 ₁, 271 ₁, and 272 ₁.

The elements and operations of memory device 200, as described above,can allow it to have improvements over some conventional memory devices.For example, memory device 200 can have fewer (e.g., 50% fewer) drivercircuits for a given memory storage capacity in comparison with someconventional memory devices (e.g., conventional memory devices withoutmultiple decks of memory cells). Fewer driver circuits can allow memorydevice 200 to have a relatively smaller device size (e.g., chip size)than some convention memory devices. In another example, the multi-deckstructure of memory device 200 allows it to have a relatively shortercontrol gates (e.g., control gates 240 ₀, 241 ₀, 242 ₀, and 243 ₀) thansome conventional memory devices for a given memory storage capacity.This can lead to an improvement in at least part of a memory operation(e.g., shorter access time in read or write operation) of memory device200. In another example, respective drain select lines (e.g., drainselect lines 284, 285, and 286 in FIG. 2 ) of different portions in themulti-deck structure of each of the blocks (e.g., block 290) of memorydevice 200 are electrically coupled to each other. Thus, a relativelylarger memory unit (e.g., larger page size) can be accessed in a memoryoperation (e.g., read or write operation) of memory device 200 incomparison with some conventional memory devices. In a further example,each of the memory cell strings in the Y-direction (e.g., memory cellstrings 231, 234, and 237 in portion 290 ₁ of FIG. 2 ) is coupled to aseparate data lines (e.g., one of data lines 270 ₁, 271 ₁, and 272 ₁).This can allow memory device 200 to provide an optimal (e.g., maximum)access unit (e.g., page size) among the memory cell strings in thememory cell block of memory device 200 in comparison with someconventional memory devices.

FIG. 3 shows a schematic diagram of a portion of memory device 200 ofFIG. 2 including details of driver circuit 240 and associated conductivelines coupled to driver circuit 240, according to some embodimentsdescribed herein. FIG. 3 also shows the portion of memory device 200including memory cell strings 231, 232, and 233 and associatedelectrical connections. Other memory cell strings (shown in FIG. 2 ) ofmemory device 200 can have similar electrical connections. Further,memory cell strings (shown in FIG. 2 ) of memory device 200 can becoupled to driver circuit 240 in ways similar to that of memory cellstrings 231, 232, and 233 are coupled to driver circuit 240.

As shown in FIG. 3 , driver circuit 240 can include transistors (e.g.,high-voltage drive transistor) T0 through T7. Transistors TO through T7can have a transistor gate 340 (e.g., a common gate, which is common totransistors TO). Thus, transistors TO through T7 can be controlled(e.g., turned on at the same time or turned off at the same time) usingthe same transistor gate (e.g., transistor gate 340).

Memory device 200 can include conductive lines 350 through 357, each ofwhich can carry a signal (e.g., voltage signal, which is different froma data signal). As an example, conductive lines 350 through 337 cancarry signals (e.g., voltage signal) V0 through V7, respectively. Drivercircuit 240 can use transistors T0 through T7 to provide (e.g., drive)signals from conductive lines 350 through 357 to respective elements(e.g., respective control lines and drain/source select lines) ofportions 290 ₀ and 290 ₁ of block 290. For example, driver circuit 240can use transistor T0 to provide signal V0 to select line 280 of bothportions 290 ₀ and 290 ₁. Driver circuit 240 can use transistors T1, T2,T3, and T4 to provide signals V1, V2, V3, and V4 to respective accesslines 250, 251, 252, and 253, and then to control gates 240 ₀, 241 ₀,242 ₀, and 243 ₀, respectively, and to control gates 240 ₁, 241 ₁, 242₁, and 243 ₁, respectively. Driver circuit 240 can use transistors T5,T6, and T7 to provide signals V5, V6, and V7 to select lines 286, 285,and 284, respectively, of both portions 290 ₀ and 290 ₁.

During an operation (e.g., a read or write operation) of memory device200, if block 290 is selected to be accessed (to operate on memory cells210, 211, 212, and 213 of block 290), signal BLK_SEL can be activated.In this example, transistors TO through T7 can be turned on (e.g.,concurrently turned on by signal BLK_SEL) to establish circuit paths(e.g., current paths) between conductive lines 350 through 357 andrespective select line 280, access lines 250, 251, 252, and 253, andselect lines 286, 285, and 284 through transistors T1 through T7,respectively. This allows signals V0 through V7 to be applied to selectline 280, access lines 250, 251, 252, and 253, and select lines 286,285, and 284, respectively. In an operation (e.g., read, write, orerase) performed on block 290, signals V0 through V7 can have differentvalues (e.g., voltage values) and two or more of signals V0 through V7can have the same value, depending on which operation memory device 200performs and which memory cells among memory cells 210, 211, 212, and213 are selected. The voltage values of signals V0 through V7 can be anycombination of 0V (e.g., ground potential), the value of the supplyvoltage (e.g., Vcc) of memory device 200, and a value greater than thevalue of the supply voltage of memory device 200.

As shown in FIG. 3 , data line 270 ₀ of portion 290 ₀ of block 290 anddata line 270 ₁ of portion 290 ₁ of block 290 can be coupled todifferent buffer circuits (e.g., buffer circuit 220L.0 and 220R.0,respectively, which are also shown in FIG. 2 ). This connection andstructure (as shown in FIG. 3 ) allow information read from a memorycell of a selected memory cell string (e.g., one of memory cell strings231, 232, and 233) of portion 290 ₀, and information read from a memorycell of a selected memory cell string (e.g., one of memory cell strings231, 232, and 233) of portion 290 ₁ to be concurrently passed to buffercircuits 220L.0 and 220R.0, respectively, in a read operation. In awrite operation, information to be stored in a memory cell of a selectedmemory cell string (e.g., one of memory cell strings 231, 232, and 233)of portion 290 ₀, and information to be stored in a memory cell of aselected memory cell string (e.g., one of memory cell strings 231, 232,and 233) of portion 290 ₁ can be based on buffer circuits 220L.0 and220R.0, respectively.

FIG. 4 shows a perspective view of a structure of memory device 200 ofFIG. 2 including blocks (memory cell blocks) 290, 291, 292, and 293,according to some embodiments described herein. Memory device 200 caninclude numerous other blocks (e.g., 1048 blocks or a different numberof blocks). As shown in FIG. 4 , blocks 290 and 293 can be located attwo respective edges (e.g., left and right edges opposite from eachother in the X-direction) of each of decks 215 ₀ and 215 ₁. Other blocks(e.g., blocks 291 through 292) of memory device 200 can be locatedbetween blocks 290 and 293. For simplicity, FIG. 4 shows four blocks290, 291, 292, and 293 of memory device 200.

For simplicity, FIG. 4 omits driver circuit 240 and other drivercircuits of memory device 200. FIG. 4 also omits line (e.g., sourceplate) 299 ₀ of deck 215 ₀ and line (e.g., source plate) 299 ₁ of deck215 ₁. FIG. 6 (described below) shows an example location for the drivercircuits and the source plates of memory device 200.

As shown in FIG. 4 , memory device 200 can include a substrate 490 wherebuffer circuitries 220L and 220R can be located (e.g., formed in).Substrate 490 can include a monocrystalline (also referred to assingle-crystal) semiconductor material (e.g., single-crystal silicon).The monocrystalline semiconductor material of substrate 490 can includeimpurities, such that substrate 490 can have a specific conductivitytype (e.g., p-type). Buffer circuitries 220L and 220R can be located inopposite portions (e.g., left and right portions in the X-direction) ofsubstrate 490. Buffer circuitries 220L.0, 220L. 1, 220R.0, 220R.1, and220R.2 are shown in FIG. 4 . Buffer circuitry 220L.2 is hidden from theview of FIG. 4 .

Deck 215 ₀ can be formed over substrate 490 (e.g., over buffercircuitries 220L and 220R) of memory device 200. Deck 215 ₁ can beformed over deck 215 ₀. Each of blocks 290, 291, 292, and 293 canincludes a portion of deck 215 ₀ and a portion of deck 215 ₁. Forsimplicity, FIG. 4 shows labels for only portions 290 ₀ and 290 ₁ ofblock 290.

For simplicity, detailed descriptions for the same elements of memorydevice 200 are given the same labels throughout the figures (FIG. 2through FIG. 7 ) of the drawings and their description are not repeated.Some of the elements of memory device 200 may be shown in some of thefigures of drawings and omitted from some other figures in the drawings.For example, FIG. 4 omits control gates associated with signals WL2 andWL3 in each of portions 290 ₀ and 290 ₁. The omitted control gates canbe between the control gate associated with signal WL1 and the controlgate associated with signal WL126. FIG. 4 shows control gates associatedwith signals WL126 and WL127 in each of portions 290 ₀ and 290 ₁ toindicate that each of portions 290 ₀ and 290 ₁ of block 290 can include128 control gates (e.g., control gates 240 ₀ through 240 ₁₂₇, notlabeled) associated with 128 corresponding signals (e.g., word linesignals WL0, WL1 through WL126, and WL127). Similarly, in the examplestructure of memory device 200 of FIG. 4 , each of blocks 291, 292, and293 can include the same number of control gates as that of block 290(e.g., control gates 240 ₀ through 240 ₁₂₇, not labeled, in each of thetop and bottom portions of each of blocks 291, 292, and 293).

FIG. 4 shows the structure of memory device 200 including four drainselect lines (associated with signals SGD0, SGD1, SGD2, and SGD3) ineach of portions 290 ₀ and 290 ₁ of block 290 (and each of blocks 291,292, and 293) as an example. However, the number of drain select linesin each of portions 290 ₀ and 290 ₁ of block 290 can vary. The drainselect lines associated with signals SGD0, SGD1, and SGD2 areschematically shown in FIG. 2 and FIG. 3 . The drain select lineassociated with signal (e.g., drain select line signal) SGD3 in FIG. 4is not schematically shown in FIG. 2 and FIG. 3 .

In FIG. 4 , conductive lines (thin lines) extending in the Z-direction(between portions 290 ₀ and 290 ₁ of block 290) symbolically representelectrical connections (e.g., conductive lines) between two respectiveelements in each of blocks 290, 291, 292, and 293. Each of suchelectrical connections can include a structure of conductive material(or materials) that can include, e.g., metal, conductively dopedpolysilicon, or other conductive materials to provide an electricalconduction (e.g., a current path) between two elements connected by theelectrical connection. For example, in FIG. 4 , conductive line 284′ canrepresent an electrical connection between two drain select lines 284(not labeled) associated with signal SGD0 of respective portion 290 ₀and 290 ₁. In another example, conductive line 251′ can represent anelectrical connection between two control gates 241 ₀ and 241 ₁ (notlabeled) associated with signal WL1 of respective portions 290 ₀ and 290₁.

As shown in FIG. 4 , each of control gates (not labeled) associated withsignals WL0, WL1 through WL126, and WL127 can include a structure (e.g.,a piece, a layer, or a level) of conductive material (e.g., metal,conductively doped polysilicon, or other conductive materials). Each ofthe source select lines (associated with signal SGS) can include astructure similar to that of each of the control gates. Each of thedrain select lines (associated with signals SDG0, SGD1, SGD2, and SGD3)can include a structure (e.g., a piece, a layer, or a level) ofconductive material (e.g., metal, conductively doped polysilicon, orother conductive materials) having a length extending in theY-direction.

As shown in FIG. 4 , data lines 270 ₀, 271 ₀, and 272 ₀ can be locatedbetween decks 215 ₀ and 215 ₁. Each of data lines 270 ₀, 271 ₀, and 272₀ can have a length extending in a direction (e.g., the X-direction)from one side (e.g., left side adjacent the left edge) of each of decks215 ₀ and 215 ₁ to another side (e.g., right side adjacent the rightedge) of each of decks 215 ₀ and 215 ₁, Data lines 270 ₀, 271 ₀, and 272₀ can be coupled (e.g., directly coupled) to buffer circuits 220L.0,220L.1, and 220L.2 through conductive paths 270′₀, 271′₀, and 272′₀,respectively. Conductive paths 270′₀, 271′₀, and 272′₀ can extend in adirection (e.g., Z-direction) perpendicular to substrate 490.

Data lines 270 ₁, 271 ₁, and 272 ₁ can be located over decks 215 ₁. Eachof data lines 270 ₁, 271 ₁, and 272 ₁ can have a length extending in theX-direction. Data lines 270 ₁, 271 ₁, and 272 ₁ can be coupled (e.g.,directly coupled) to buffer circuits 220R.0, 220R1, and 220R.2 throughconductive paths 270′₁, 271′₁, and 272′₁, respectively. Conductive paths270′₁, 271′₁, and 272′₁ can extend in a direction (e.g., Z-direction)perpendicular to substrate 490.

As shown in FIG. 4 , conductive paths 270′₀, 271′₀, and 272′₀ can belocated on a side (e.g., adjacent the left edge) of each of decks 215 ₀and 215 ₁. Conductive paths 270′₁, 271′₁, and 272′₁ can be located onanother side (e.g., right side opposite from the left side (e.g.,adjacent the right edge) of each of decks 215 ₀ and 215 ₁ in theX-direction, which is perpendicular to the direction (e.g., Z-direction)from deck 215 ₀ to deck 215 ₁.

Conductive paths 270′₀, 271′₀, and 272′₀ are physically separated from(e.g., electrically unconnected to) conductive paths 270′₁, 271′₁, and272′₁. Deck 215 ₀ does not share conductive paths 270′₀, 271′₀, and272′₀ with deck 215 ₁. Deck 215 ₁ does not share conductive paths 270′₁,271′₁, and 272′₁ with deck 215 ₀. This allows memory device 200 toconcurrently access both portions (e.g., top and bottom portions) of aselected block (e.g., portions 290 ₀ and 290 ₁ of block 290) in the sameoperation (e.g., the same read operation, the same write operation, orthe same erase operation).

FIG. 4 shows example locations of buffer circuits 220L.0, 220L.1, and220L.2 where at least a portion of each of buffer circuits 220L.0,220L.1, and 220L.2 is under block 290 (e.g., located in a portion (e.g.,left portion) of substrate 490 under block 290), and example locationsof buffer circuits 220R.0, 220R.1, and 220R.2 where at least a portionof each of buffer circuits 220R.0, 220R.1, and 220R.2 is under block 293(e.g., located in a portion (e.g., right portion) of substrate 490 underblock 293). However, buffer circuits 220L.0, 220L.1, and 220L.2 andbuffer circuits 220R.0, 220R.1, and 220R.2 can be located at differentlocations of substrate 490. In an alternative structure of memory device200, some or all of buffer circuits 220L.0, 220L.1, and 220L.2 andbuffer circuits 220R.0, 220R.1, and 220R.2 can be located at locationsnot under the memory cells (e.g., located outside the memory array) ofmemory device 200.

FIG. 5 shows a side view (e.g., cross-sectional view) of a portion ofmemory device 200 including blocks 290 and 291, according to someembodiments described herein. The same elements of memory device 200 inFIG. 2 through FIG. 5 are given the same labels and detaileddescriptions for the same elements of memory device 200 are notrepeated.

As shown in FIG. 5 , memory device 200 can include a dielectricstructure (e.g., silicon dioxide) 510 between deck 215 ₀ and deck 215 ₁.Each of blocks 290 and 291 can include a portion (e.g., top portion) indeck 215 ₁ and a portion (e.g., bottom portion) in deck 215 ₀. Forexample, block 291 can include a portion (e.g., top portion) 291 ₁ thatis part of deck 215 ₁ and a portion (e.g., bottom portion) 291 ₀ that ispart of deck 215 ₀.

FIG. 5 omits electrical connections between the drain select lines(associated with signals SGD0, SGD1, SGD2, and SGD3) of portion 290 ₀ ofblock 290 and the drain select lines (associated with signals SGD0,SGD1, SGD2, and SGD3) of portion 290 ₁ of block 290. FIG. 5 also omitselectrical connections between the drain select lines (associated withsignals SGD0, SGD1, SGD2, and SGD3) of portion 291 ₀ of block 291 andthe drain select lines (associated with signals SGD0, SGD1, SGD2, andSGD3) of portion 291 ₁ of block 291. The drain select lines (associatedwith signals SGD0, SGD1, SGD2, and SGD3 in block 290) of block 290 areelectrically separated from the drain select lines (associated withsignals SGD0, SGD1, SGD2, and SGD3 in block 291) of the other block.

As shown in FIG. 5 , each of blocks 290 and 291 can have its own controlgates, such that the control gates (associated with signals WL0, WL1through WL126, and WL127) of block 290 can be electrically separatedfrom the control gates (associated with signals WL0, WL1 through WL126,and WL127) of block 291.

As described above with reference to FIG. 2 , memory device 200 caninclude a separate driver circuit for each block of memory device 200.FIG. 5 shows two driver circuits 240 and 241 associated with blocks 290and 291, respectively. Driver circuits 240 and 241 can be locatedadjacent each other in the X-direction. For simplicity, FIG. 5 omitselectrical connections between driver circuit 240 and other componentsof block 290, and electrical connections between driver circuit 241 andother components of block 291.

Each of driver circuits 240 and 241 can provide signals to acorresponding block. As shown in FIG. 5 , driver circuit 240 can providesignals SGD0 through SGD3, WL0 through WL127, and SGS to block 290.Driver circuit 241 can provide signals SGD0 through SGD3, WL0 throughWL127, and SGS to block 291. For simplicity, FIG. 5 shows the samelabels for the signals in blocks 290 and 291. However, signals SGD0through SGD3, WL0 through WL127, and SGS provided to block 290 (bydriver circuit 240) are different from signals SGD0 through SGD3, WL0through WL127, and SGS provided to block 291 (by driver circuit 241).

As shown in FIG. 5 , each of blocks 290 and 291 can include pillars(e.g., pillars 509) extending in the Z-direction (e.g., a vertical bodyperpendicular to substrate 490). Only four pillars 509 are labeled inFIG. 5 to avoid crowding FIG. 5 . As described in more detailed belowwith reference to FIG. 7 , the memory cells of a memory cell string ofmemory device 200 can be located along the length (e.g., in theZ-direction) of a respective pillar among pillars 509.

FIG. 6 shows another perspective view including locations of drivercircuits and page buffer circuits of memory device 200 of FIG. 2 throughFIG. 5 , according to some embodiments described herein. As shown inFIG. 6 , decks 215 ₀ and 215 ₁ can be part of a memory array 601 ofmemory device 200. Thus, the blocks (only blocks 290, 291, 292, and 293are labeled) of memory device 200 can be included in memory array 601.

As shown in FIG. 6 , buffer circuitries 220L and 220R can be located onopposite sides (in the X-direction) of substrate 490. For example,buffer circuitry 220L can be located in a portion of substrate 490 ofmemory device 200 under (e.g., directly underneath) memory array 601 andon a side (e.g., left side) of memory array 601 (e.g., on the left sideof each of decks 215 ₀ and 215 ₁). Buffer circuitry 220R can be locatedin another a portion of substrate 490 of memory device 200 under (e.g.,directly underneath) memory array 601 and on another side (e.g., rightside) of memory array 601 (e.g., on the right side of each of decks 215₀ and 215 ₁).

As shown in FIG. 6 , memory device 200 can include driver circuitry 640that can be located in a portion of substrate 490 adjacent (e.g., in theY-direction and outside the footprint of) the portions of substrate 490where buffer circuitries 220L and 220R are located. Driver circuitry 640can include driver circuits 240 and 241 (described above with referenceto FIG. 5 ). FIG. 6 also shows other driver circuits (e.g., drivercircuits 242 and 243) of driver circuitry 640. As described above, eachblock among the blocks of memory device 200 can have its own drivercircuit. In FIG. 6 , for example, driver circuits 240, 241, 242, and 243can be used to drive signals to the elements (e.g., control gates andselect lines, not shown in detail) of blocks 290, 291, 292, and 293,respectively.

FIG. 7 shows a side view of a structure of a portion of memory device200 of FIG. 2 including more details of pillars 509 and of memory cells210, 211, 212, and 213 of block 290, according to some embodimentsdescribed herein. Only four pillars 509 are labeled in FIG. 7 to avoidcrowding FIG. 7 . As shown in FIG. 7 , decks 215 ₀ and 215 ₁ can beformed over substrate 490 (e.g., formed one over another (stacked) inthe Z-direction over substrate 490).

As shown in FIG. 7 , memory cells 210, 211, 212, and 213 of portion 290₀ of block 290 can be located in different levels 721, 722, 723, and724, respectively, of memory device 200 in the Z-direction. Memory cells210, 211, 212, and 213 of portion 290 ₁ of block 290 can be respectivelylocated in different levels 725, 726, 727, and 728 of memory device 200in the Z-direction.

Each of memory cell strings 231, 232, and 233 of each of portions 290 ₀or 290 ₁ of block 290 can include at least part of a respective pillaramong pillars 509. Pillar 509 can include pillar portions 706, 707, and708 between a respective data line (data line 270 ₀ or 270 ₁) and arespective line (e.g., source line or source) 299 ₀ or 299 ₁. Pillar 509can be configured to provide a conduction of current (e.g., to form aconductive structure (e.g., channel)) between the respective data line(data line 270 ₀ or 270 ₁) and a respective source (source 299 ₀ or 299₁). Pillar portions 706 and each of pillar portions 707 and 708 caninclude materials of different conductivity types. For example, pillarportion 706 can include a semiconductor material of p-type, and each ofpillar portions 707 and 708 can include a semiconductor material ofn-type. The semiconductor material can include polycrystalline silicon(polysilicon).

As shown in FIG. 7 , control gates 240 ₀, 241 ₀, 242 ₀, and 243 ₀ indeck 215 ₀ can be located along respective segments of pillar portion706 of the pillar (one of pillars 509) of a respective memory cellstring among memory cell strings 231, 232, and 233 of portion 290 ₀ ofblock 290. Control gates 240 ₀, 241 ₀, 242 ₀, and 243 ₀ can be locatedin the Z-direction in the same levels (e.g., 721, 722, 723, and 724)where memory cells 210, 211, 212, and 213 of portion 290 ₀ of block 290are located.

Similarly, control gates 240 ₁, 241 ₁, 242 ₁, and 243 ₁ in deck 215 ₁can be located along respective segments of pillar portion 706 of thepillar (one of pillars 509) of a respective memory cell string amongmemory cell strings 231, 232, and 233 of portion 290 ₁ of block 290.Control gates 240 ₁, 241 ₁, 242 ₁, and 243 ₁ can be located in theZ-direction in the same levels (e.g., 725, 726, 727, and 728) wherememory cells 210, 211, 212, and 213 of portion 290 ₁ of block 290 arelocated.

Each of decks 215 ₀ and 215 ₁ can include materials 703, 704, and 705formed adjacent a respective pillar among pillars 509 of each of portion290 ₀ and 290 ₁ of block 290. For simplicity, the following descriptionfocuses on materials 703, 704, and 705 in portion 290 ₀ of block 290.Materials 703, 704, and 705 in portion 290 ₁ of block 290 have similarstructures and materials.

In portion 290 ₀ of block 290, material 705 can be formed between arespective pillar among pillars 509 of a corresponding memory cellstring (memory cell string 231, 232, or 233) and select line (e.g.,source select line) 280. Material 705 can also be formed between arespective pillar among pillars 509 of a corresponding memory cellstring (memory cell string 231, 232, or 233) and each of select lines(e.g., drain select lines) 284, 285, and 286. Material 705 can be usedas a gate oxide for each of select transistors (e.g., source selecttransistors) 261, 262, and 263, and each of select transistors (e.g.,drain select transistors) 264, 265, and 266.

The combination of materials 703, 704, 705 in portion 290 ₀ of block 290can be formed between pillar portion 706 of a corresponding pillar andeach of control gates 240 ₀, 241 ₀, 242 ₀, 243 ₀. The combination ofmaterials 703, 704, 705 can form part of the structure of a memory cell(e.g., memory cell 210, 211, 212, or 213) of portion 290 ₀ of block 290.For example, the combination of materials 703, 704, and 705 can be partof a TANOS (TaN, Al₂O₃, Si₃N₄, SiO₂, Si) structure of each of memorycells 210, 211, 212, and 213 of each of portion 290 ₀ and 290 ₁ of block290. In this example, material 703 (e.g., interpoly dielectrics) caninclude a charge-blocking material or materials (e.g., a dielectricmaterial such as TaN and Al₂O) that is capable of blocking a tunnelingof a charge. Material 704 can include a charge storage element (e.g.,charge storage material or materials, such as Si₃N₄) that can provide acharge storage function (e.g., trap charge) to represent a value ofinformation stored in memory cells 210, 211, 212, or 213. Material 705can include a tunnel dielectric material or materials (e.g., SiO₂) thatis capable of allowing tunneling of a charge (e.g., electrons). As anexample, material 705 can allow tunneling of electrons from pillarportion 706 to material 704 during a write operation and tunneling ofelectrons from material 704 to pillar portion 706 during an eraseoperation of memory device 200.

In another example, the combination of materials 703, 704, and 705 canbe part of a SONOS (Si, SiO₂, Si3N₄, SiO₂, Si) structure of each ofmemory cells 210, 211, 212, and 213 of each of portion 290 ₀ and 290 ₁of block 290. In a further example, the combination of materials 703,704, and 705 can be part of a floating gate structure of each of memorycells 210, 211, 212, and 213 of each of portion 290 ₀ and 290 ₁ of block290.

As shown in FIG. 7 , buffer circuit 220L.0 (which is one of buffercircuits of buffer circuitry 220L) can be located in (e.g., formed in) aportion of (e.g., left portion) of substrate 490. Buffer circuit 220R.0(which is one of buffer circuits of buffer circuitry 220R) can belocated in (e.g., formed in) another portion of (e.g., right portion) ofsubstrate 490. Thus, buffer circuitry 220L.0 and 220R.0 can be formed onopposite portions (e.g., left and right portions) in the X-direction ofsubstrate 490.

As shown in FIG. 7 , data line 270 ₀ can have a length extending in adirection (e.g., the X-direction) from a portion of substrate 490 (e.g.,the portion where buffer circuit 220L.0 is located) to another portionof substrate 490 (e.g., portion where buffer circuit 220R.0 is located).Similarly, data line 270 ₁ can have a length extending in the direction(e.g., X-direction) from the portion of substrate 490 where buffercircuit 220L.0 is located to the portion of substrate 490 where buffercircuit 220R.0 is located. Each of the other data lines (e.g., datalines 271 ₀, 272 ₀, 271 ₁, and 272 ₁ shown in FIG. 4 ) of memory device200 can have a length extending in the direction (e.g., X-direction)from the portion of substrate 490 where buffer circuit 220L.0 is locatedto the portion of substrate 490 where buffer circuit 220R.0 is located.

As shown in FIG. 7 , data line 270 ₀ can be coupled (e.g., directlycoupled) to buffer circuit 220L.0 through (e.g., directly through)conductive path 270′₀. Conductive path 270′₀ can be considered as partof data line 270 ₀, such that the material of conductive path 270′₀ candirectly contact the material of data line 270 ₀. Data line 270 ₁ can becoupled (e.g., directly coupled) to buffer circuit 220R.0 through (e.g.,directly through) a conductive path 270′₁. Conductive path 270′₁ can beconsidered as part of data line 270 ₁, such that the material ofconductive path 270′₁ can directly contact the material of data line 270₁. Each of conductive paths 270′₀ and 270′₁ can have a length extendingin a direction (e.g., Z-direction) from deck 215 ₀ to deck 215 ₁ (e.g.,extending vertically in the Z-direction). Each of conductive paths 270′₀and 270′₁ can include a conductive material (or conductive materials)that is located (e.g., formed vertically) over substrate 490, such asconductively doped polycrystalline silicon, metal, or other conductivematerials.

As shown in FIG. 7 , conductive paths 270′₀ and 270′₁ are physicallyseparated from each other (e.g., electrically unconnected to eachother), and data lines 270 ₀ and 270 ₁ are separately coupled to buffercircuits 220 and 221 through conductive paths 270′₀ and 270′₁,respectively. Thus, conductive paths 270′₀ and 270′₁ are not shared byportions 290 ₀ and 290 ₁ of block 290. This allows memory device 200 toconcurrently access both portions 290 ₀ and 290 ₁ of block 290 in thesame operation (e.g., the same read operation, the same write operation,or the same erase operation), as described above with reference to FIG.2 through FIG. 7 .

The illustrations of apparatuses (e.g., memory devices 100 and 200) andmethods (e.g., operating methods associated with memory devices 100 and200 and methods (e.g., processes) of forming at least a portion ofmemory devices 100 and 200) are intended to provide a generalunderstanding of the structure of various embodiments and are notintended to provide a complete description of all the elements andfeatures of apparatuses that might make use of the structures describedherein. An apparatus herein refers to, for example, either a device(e.g., any of memory devices 100 and 200) or a system (e.g., a computer,a cellular phone, or other electronic system) that includes a devicesuch as any of memory devices 100 and 200.

Any of the components described above with reference to FIG. 1 throughFIG. 7 can be implemented in a number of ways, including simulation viasoftware. Thus, apparatuses (e.g., memory devices 100 and 200 or part ofeach of these memory devices, including a control unit in these memorydevices, such as control unit 118 (FIG. 1 )) described above may all becharacterized as “modules” (or “module”) herein. Such modules mayinclude hardware circuitry, single and/or multi-processor circuits,memory circuits, software program modules and objects and/or firmware,and combinations thereof, as desired and/or as appropriate forparticular implementations of various embodiments. For example, suchmodules may be included in a system operation simulation package, suchas a software electrical signal simulation package, a power usage andranges simulation package, a capacitance-inductance simulation package,a power/heat dissipation simulation package, a signaltransmission-reception simulation package, and/or a combination ofsoftware and hardware used to operate or simulate the operation ofvarious potential embodiments.

Memory devices 100 and 200 may be included in apparatuses (e.g.,electronic circuitry) such as high-speed computers, communication andsignal processing circuitry, single or multi-processor modules, singleor multiple embedded processors, multicore processors, messageinformation switches, and application-specific modules includingmultilayer, multichip modules. Such apparatuses may further be includedas subcomponents within a variety of other apparatuses (e.g., electronicsystems), such as televisions, cellular telephones, personal computers(e.g., laptop computers, desktop computers, handheld computers, tabletcomputers, etc.), workstations, radios, video players, audio players(e.g., MP3 (Motion Picture Experts Group, Audio Layer 3) players),vehicles, medical devices (e.g., heart monitor, blood pressure monitor,etc.), set top boxes, and others.

The embodiments described above with reference to FIG. 1 through FIG. 7include apparatuses and methods of using the apparatuses. One of theapparatuses includes a substrate, a first deck including first memorycell strings located over the substrate, a second deck including secondmemory cell strings and located over the first deck, first data lineslocated between the first and second decks and coupled to the firstmemory cell strings, second data lines located over the second deck andcoupled to the second memory cell strings, and first and secondcircuitries. The first and second data lines extending in a directionfrom a first portion of the substrate to a second portion of thesubstrate. The first buffer circuitry is located in the first portion ofthe substrate under the first memory cell strings of the first deck andcoupled to the first data lines. The second buffer circuitry is locatedin the second portion of the substrate under the first memory cellstrings of the first deck and coupled to the second data lines. Otherembodiments including additional apparatuses and methods are described.

In the detailed description and the claims, the term “on” used withrespect to two or more elements (e.g., materials), e.g., one “on” theother, means at least some contact between the elements (e.g., betweenthe materials). The term “over” means the elements (e.g., materials) arein close proximity, but possibly with one or more additional interveningelements (e.g., materials) such that contact is possible but notrequired. Neither “on” nor “over” implies any directionality as usedherein unless stated as such.

In the detailed description and the claims, a list of items joined bythe term “at least one of” can mean any combination of the listed items.For example, if items A and B are listed, then the phrase “at least oneof A and B” means A only; B only; or A and B. In another example, ifitems A, B, and C are listed, then the phrase “at least one of A, B andC” means A only; B only; C only; A and B (excluding C); A and C(excluding B); B and C (excluding A); or all of A, B, and C. Item A caninclude a single element or multiple elements. Item B can include asingle element or multiple elements. Item C can include a single elementor multiple elements.

In the detailed description and the claims, a list of items joined bythe term “one of” can mean only one of the list items. For example, ifitems A and B are listed, then the phrase “one of A and B” means A only(excluding B), or B only (excluding A). In another example, if items A,B, and C are listed, then the phrase “one of A, B and C” means A only; Bonly; or C only. Item A can include a single element or multipleelements. Item B can include a single element or multiple elements. ItemC can include a single element or multiple elements. In the detaileddescription and the claims, a list of items joined by the term “at leastone of” can mean any combination of the listed items. For example, ifitems A and B are listed, then the phrase “at least one of A and B” canmean A only; B only; or A and B. In another example, if items A, B, andC are listed, then the phrase “at least one of A, B and C” can mean Aonly; B only; C only; A and B (without C); A and C (without B); B and C(without A); or A, B, and C. Each of items A, B, and C can include asingle element (e.g., a circuit element) or a plurality of elements(e.g., circuit elements).

The above description and the drawings illustrate some embodiments ofthe invention to enable those skilled in the art to practice theembodiments of the invention. Other embodiments may incorporatestructural, logical, electrical, process, and other changes. Examplesmerely typify possible variations. Portions and features of someembodiments may be included in, or substituted for, those of others.Many other embodiments will be apparent to those of skill in the artupon reading and understanding the above description.

What is claimed is:
 1. An apparatus comprising: a first deck includingfirst memory cell strings; a second deck located over the first deck,the second deck including second memory cell strings; first data lineslocated between the first and second decks and coupled to the firstmemory cell strings; second data lines located over the second deck andcoupled to the second memory cell strings, the second data lineselectrically separated from the first data lines; first access lineslocated on the first deck, and second access located on the second deck;a first memory cell block coupled to the first access lines andincluding a first portion located in the first deck and a second portionlocated in the second deck, the first portion of the first memory cellblock including a first portion of the first memory cell strings, thesecond portion of the first memory cell block including a first portionof the second memory cell strings; a second memory cell block coupled tothe second access lines and including a first portion located in thefirst deck and a second portion located in the second deck, the firstportion of the second memory cell block including a second portion ofthe first memory cell strings, the second portion of the second memorycell block including a second of the second memory cell strings; thefirst portion of the first memory cell block sharing the first datalines with the first portion the second memory cell block; the secondportion of the first memory cell block sharing the second data lineswith the second portion the second memory cell block; first buffercircuitry located under the first memory cell strings of the first deckand coupled to the first data lines; and second buffer circuitry locatedunder the first memory cell strings of the first deck and coupled to thesecond data lines.
 2. The apparatus of claim 1, further comprising:conductive paths coupled between the first data lines and the firstbuffer circuitry; and second conductive paths coupled between the seconddata lines and the second buffer circuitry.
 3. The apparatus of claim 2,wherein the first and second conductive paths are extending in adirection from the first deck to the second deck.
 4. The apparatus ofclaim 3, wherein the first conductive paths are located on a first sideof the first deck, and the second conductive paths are located on asecond side opposite from the first side of the first deck.
 5. Theapparatus of claim 1, further comprising driver circuits located on alevel of the apparatus below a level of the first memory cell stringsand coupled to the first memory cell strings and the second memory cellstrings.
 6. The apparatus of claim 5, wherein the driver circuits arelocated adjacent the first buffer circuitry and adjacent the secondbuffer circuitry.
 7. An apparatus comprising: a first portion of amemory cell block, the first portion of the memory cell block includingfirst memory cell strings; a second portion of the memory cell blocklocated over the first portion of memory cell block, the second portionof the memory cell block including second memory cell strings; firstdata lines located between the first and second portions of the memorycell block; first select transistors, each of the first selecttransistors located between a respective data line of the first datalines and a respective memory cell string of the first memory cellstrings; second data lines located over the second portion of the memorycell block; second select transistors, each of the second selecttransistors located between a respective data line of the second datalines and a respective memory cell string of the second memory cellstrings; select lines, each of the select lines coupled to a respectiveselect transistor of the first select transistors and a respectiveselect transistor of the second select transistors; first access linescoupled to the first memory cell strings; and second access linescoupled to the second memory cell strings, the second access linesseparated from the first access lines.
 8. The apparatus of claim 7,wherein the first and second data lines extend in a directionperpendicular to a direction from the first portion of the memory cellblock to the second portion of the memory cell block.
 9. The apparatusof claim 7, wherein the second access lines are located over the firstaccess lines.
 10. The apparatus of claim 7, further comprising: firstbuffer circuits, each of the first buffer circuits coupled to arespective data line of the first data lines; and second buffercircuits, each of the second buffer circuits coupled to a respectivedata line of the second data lines.
 11. The apparatus of claim 10,wherein a direction from the first buffer circuits to the second buffercircuits is perpendicular to a direction from the first portion of thememory cell block to the second portion of the memory cell block. 12.The apparatus of claim 7, wherein the memory cell block is a firstmemory cell block, and the apparatus further comprises: a first portionof a second memory cell block, the first portion of the second memorycell block including first additional memory cell string; a secondportion of the second memory cell block located over the first portionof the second memory cell block, the second portion of the second memorycell block including second additional memory cell strings; firstadditional select transistors, each of the first additional selecttransistors located between a respective data line of the first datalines and a respective memory cell string of the first additional memorycell strings; second additional select transistors, each of the secondadditional transistors located between a respective data line of thesecond data lines and a respective memory cell string of the secondadditional memory cell strings; and additional select lines, each of theadditional select lines coupled to a respective select transistor of thefirst additional select transistors and a respective select transistorof the second additional select transistors.
 13. The apparatus of claim12, further comprising: a first driver circuit coupled to the firstmemory cell block and located on a level of the apparatus below a levelof the first memory cell strings; and a second driver circuit coupled tothe second memory cell block and located on a level of the apparatusbelow a level of the first memory cell strings.
 14. An apparatuscomprising: a first deck located over the substrate, the first deckincluding first memory cell strings; a second deck located over thefirst deck, the second deck including second memory cell strings; firstdata lines located between the first and second decks and coupled to thefirst memory cell strings; second data lines located over the seconddeck and coupled to the second memory cell strings, the first and seconddata lines extending in a direction from a first side of the first deckto a second side of the first deck; memory cell blocks, each of thememory cell blocks including a first portion and a second portion, thefirst portion including a respective portion of the first memory cellstrings, the second portion including a respective portion of the secondmemory cell strings; first conductive paths located on the first side ofthe first deck and coupled to the first data lines, the first conductivepaths extending in a direction from the first deck to the second deck;first buffer circuitry coupled to the first conductive paths; secondconductive paths located on the second side of the first deck andcoupled to the second data lines, the second conductive paths extendingin the direction from the first deck to the second deck; second buffercircuitry coupled to the second conductive paths; driver circuitsadjacent the first and second buffer circuitries, each of the drivercircuits coupled to a respective memory cell block of the memory cellblocks; first access lines located on the first deck, wherein therespective portion of the first memory cell strings of each of theblocks is coupled to a respective portion of the first access lines; andsecond access lines located on the second deck, wherein the respectiveportion of the second memory cell strings of each of the blocks iscoupled to a respective portion of the second access lines.
 15. Theapparatus of claim 12, wherein a number of the first data lines is equalto a number of the second data lines.
 16. The apparatus of claim 12,wherein the first buffer circuitry and the second buffer circuitry arelocated in a substrate under the first memory cell strings.
 17. Theapparatus of claim 16, wherein the first buffer circuitry is located ina first portion of the substrate on the first side of the first deck,and the second buffer circuitry is located in a second portion of thesubstrate on the second side of the first deck.
 18. The apparatus ofclaim 17, wherein the driver circuits include first driver circuitslocated in the substrate adjacent the first buffer circuitry, and thedriver circuits includes second driver circuits located in the substrateadjacent the second buffer circuitry.
 19. The apparatus of claim 18,further comprising: first select transistors located between the firstdata lines and the first memory cell strings; and second selecttransistors located between the second data lines and the second memorycell strings.
 20. The apparatus of claim 19, further comprising: firstadditional select transistors the first memory cell strings and asubstrate; and second additional select transistors located between thesecond memory cell strings and the first data lines.